View KM29N32000TS_1439280.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

KM29N32000TS flash memory 1 document title 4m x 8 bit nand flash memory revision history the attached datasheets are prepared and approved by samsung electronics. samsung electronics co., ltd. reserve the right to change the specifications. samsung electronics will evaluate and reply to your requests and questions about device. if you ha ve any questions, please contact the samsung branch office near you. revision no. 0.0 1.0 1.1 remark final history data sheet, 1997 data sheet, 1998 1. changed t bers parameter : 5ms(typ.) ? 2ms(typ.) 2. removed reverse type package. 3. changed ac parameters. t wh : 10ns(min.) ? 15ns(min). t reh : 10ns(min) ? 15ns(min). data sheet, 1998 draft date april 10th 1997 april 10th 1998 july 14th 1998
KM29N32000TS flash memory 2 4m x 8 bit nand flash memory the km29n32000 is a 4m(4,194,304)x8bit nand flash mem- ory with a spare 128k(131,072)x8bit. its nand cell provides the most cost-effective solution for the solid state mass storage market. a program operation programs the 528-byte page in typically 250 m s and an erase operation can be performed in typ- ically 2ms on an 8k-byte block. data in the page can be read out at 50ns cycle time per byte. the i/o pins serve as the ports for address and data input/out- put as well as command inputs. the on-chip write controller automates all program and erase system functions, including pulse repetition, where required, and internal verify and margin- ing of data. even the write-intensive systems can take advan- tage of the km29n32000 extended reliability of 1,000,000 program/erase cycles by providing either ecc(error correction code) or real time mapping-out algorithm. these algorithms have been implemented in many mass storage applications and also the spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ecc. the km29n32000 is an optimum solution for large nonvolatile storage applications such as solid state storage, digital voice recorder, digital still camera and other portable applications requiring nonvolatility. general description features single 5.0 volt supply organization - memory cell array : (4m + 128k)bit x 8bit - data register : (512 + 16)bit x8bit automatic program and erase - page program : (512 + 16)byte - block erase : (8k + 256)byte - status register 528-byte page read operation - random access : 10 m s(max.) - serial page access : 50ns(min.) fast write cycle time - program time : 250 m s(typ.) - block erase time : 2ms(typ.) command/address/data multiplexed i/o port hardware data protection - program/erase lockout during power transitions reliable cmos floating-gate technology - endurance : 1m program/erase cycles - data retention : 10 years command register operation 44(40) - lead tsop type ii (400mil / 0.8 mm pitch) - forward type pin configuration vss cle ale we wp n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c i/o0 i/o1 i/o2 i/o3 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 vcc i/o4 i/o5 i/o6 i/o7 n.c n.c n.c n.c n.c n.c n.c n.c n.c n.c se r/ b re ce vcc 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 44(40) tsop (ii) standard type note : connect all v cc and v ss pins of each device to power supply outputs. do not leave v cc or v ss disconnected. pin name pin function i/o 0 ~i/o 7 data inputs/outputs cle command latch enable ale address latch enable ce chip enable re read enable we write enable wp write protect se spare area enable r/ b ready/busy output v cc power(+5v) v ss ground n.c no connection pin description
KM29N32000TS flash memory 3 512b column 16b column figure 1. functional block diagram figure 2. array organization note : column address : starting address of the register. 00h command(read) : defines the starting address of the 1st half of the register. 01h command(read) : defines the sarting address of the 2nd half of the register. * a 8 is initially set to "low" or "high" by the 00h or 01h command. * x can be high or low. i/o 0 i/o 1 i/o 2 i/o 3 i/o 4 i/o 5 i/o 6 i/o 7 1st cycle a 0 a 1 a 2 a 3 a 4 a 5 a 6 a 7 2nd cycle a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 16 3rd cycle a 17 a 18 a 19 a 20 a 21 *x *x *x v cc x-buffers y-gating 32m + 1m bit command 2nd half page register & s/a nand flash array (512 + 16)byte x 8192 y-gating 1st half page register & s/a i/o buffers & latches latches & decoders y-buffers latches & decoders register control logic & high voltage generator global buffers output driver v ss a 9 - a 21 a 0 - a 7 command ce re we cle ale wp i/0 0 i/0 7 v cc v ss a 8 1st half page register (=256 bytes) 2nd half page register (=256 bytes) 32m : 8k row (=512 block) 512byte 8 bit 16byte 1 block(=16 row) (8k + 256) byte i/o 0 ~i/o 7 1 page = 528 byte 1 block = 528 b x 16 pages = (8k + 256) bytes 1 device = 528b x 16pages x 512 blocks = 33 mbits column address row address (page address) page register
KM29N32000TS flash memory 4 product introduction the km29n32000 is a 33mbit(34,603,008 bit) memory organized as 8192 rows by 528 columns. spare sixteen columns are located from column address of 512 to 527. a 528-byte data register is connected to memory cell arrays accommodating data transfer between the i/o buffers and memory during page read and page program operations. the memory array is made up of 16 cells that are serially connected to form a nand structure. each of the 16 cells resides in a different page. a block consists of the 16 pa ges formed by one nand structures, totaling 528 nand structures of 16 cells. the array organization is shown in figure 2. the progra m and read opertions are executed on a page basis, while the erase operation is executed on block basis. the memory array consists of 512 separately or grouped erasable 8k-byte blocks. it indicates that the bit by bit erase operation is prohibited on the km29n32000. the km29n32000 has addresses multiplexed into 8 i/o s. this scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. command, address and data are all written throug h i/o s by bringing we to low while ce is low. data is latched on the rising edge of we . command latch enable(cle) and address latch enable(ale) are used to multiplex command and address respectively, via the i/o pins. all commands require one bus cycle except for block erase command which requires two cycles : a cycle for erase-setup and another for erase-execution after block address loading. the 4m byte physical space requires 22 addresses, thereby requiring three cycles for byte-level addressing : co l- umn address, low row address and high row address, in that order. page read and page program need the same three address cycles following the required command input. in block erase operation, however, only the two row address cycles are used. device operations are selected by writing specific commands into the command register. table 1 defines the specific commands of the km29n32000. table 1. command sets note : 1. the 00h command defines starting address on the 1st half of registers. the 01h command defines starting address on the 2nd half of registers. after data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h) on the next cycle. 2. the 50h command is valid only when the se (pin 40) is low level. function 1st. cycle 2nd. cycle acceptable command during busy sequential data input 80h - read 1 00h/01h (1) - read 2 50h (2) - read id 90h - reset ffh - o page program 10h - block erase 60h d0h erase suspend b0h - o erase resume d0h - read status 70h - o
KM29N32000TS flash memory 5 pin description command latch enable(cle) the cle input controls the path activation for commands sent to the command register. when active high, commands are latched into the command register through the i/o ports on the rising edge of the we signal. address latch enable(ale) the ale input controls the path activation for address and input data to the internal address/data register. addresses are latched on the rising edge of we with ale high, and input data is latched when ale is low. chip enable( ce ) the ce input is the device selection control. when ce goes high during a read operation the device is returned to standby mode. however, when the device is in the busy state during program or erase, ce high is ignored, and does not return the device to standby mode. write enable( we ) the we input controls writes to the i/o port. commands, address and data are latched on the rising edge of the we pulse. read enable( re ) the re input is the serial data-out control, and when active drives the data onto the i/o bus. data is valid t rea after the falling edge of re which also increments the internal column address counter by one. spare area enable( se ) the se input controls the spare area selection when se is high, the device is deselected the spare area during read1, sequential data input and page program. i/o port : i/o 0 ~ i/o 7 the i/o pins are used to input command, address and data, and to output data during read operations. the i/o pins float to high- z when the chip is deselected or when the outputs are dsabled. write protect( wp ) the wp pin provides inadvertent write/erase protection during power transitions. the internal high voltage generator is reset when the wp pin is active low. ready/ busy (r/ b ) the r/ b output indicates the status of the device operation. when low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. it is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.
KM29N32000TS flash memory 6 recommended operating conditions (voltage reference to gnd, t a =0 to 70 c) parameter symbol min typ. max unit supply voltage v cc 4.5 5.0 5.5 v supply voltage v ss 0 0 0 v dc and operating characteristics (recommended operating conditions otherwise noted.) parameter symbol test conditions min typ max unit operating current sequential read i cc1 tcycle=50ns ce =v il , i out =0ma - 15 30 ma command, address input i cc3 tcycle=50ns - 15 30 ma data input i cc4 - - 15 30 ma program i cc6 - - 15 30 ma erase i cc7 - - 25 40 ma stand-by current(ttl) i sb1 ce =v ih , wp = se =0v/v cc - - 1 ma stand-by current(cmos) i sb2 ce =v cc -0.2, wp = se =0v/v cc - 10 100 m a input leakage current i li v in =0 to 5.5v - - 10 m a output leakage current i lo v out =0 to 5.5v - - 10 m a input high voltage, all inputs v ih - 2.0 - v cc +0.5 v input low voltage, all inputs v il - -0.3 - 0.8 v output high voltage level v oh i oh =-400 m a 2.4 - - v output low voltage level v ol i ol =2.1ma - - 0.4 v output low current(r/ b ) i ol (r/ b ) v ol =0.4v 8 10 - ma absolute maximum ratings note : 1. minimum dc voltage is -0.3v on input/output pins. during transitions, this level may undershoot to -2.0v for periods <30ns. maximum dc voltage on input/output pins is v cc +0.3v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 2. permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. exposure to absolute maximum rating conditions for extended periods may affect reliability. parameter symbol rating unit voltage on any pin relative to v ss v in -0.6 to +7.0 v temperature under bias t bias -10 to +125 c storage temperature t stg -65 to +150 c short circuit output current i os 5 ma
KM29N32000TS flash memory 7 mode selection note : 1. x can be v il or v ih 2. wp should be biased to cmos high or cmos low for standby. 3. when se is high, spare area is deselected. cle ale ce we re se wp mode h l l h x x read mode command input l h l h x x address input(3clock) h l l h x h write mode command input l h l h x h address input(3clock) l l l h l/h (3) h data input l l l h l/h (3) x sequential read & data output l l l h h l/h (3) x during read(busy) x x x x x l/h (3) h during program(busy) x x x x x x h during erase(busy) x x (1) x x x x l write protect x x h x x 0v/v cc (2) 0v/v cc (2) stand-by ac test condition (t a =0 to +70 c, v cc =5v 10%, unless otherwise noted.) parameter value input pulse levels 0.4v to 2.6v input rise and fall times 5ns input and output timing levels 0.8v and 2.0v output load 1 ttl gate and cl=100pf capacitance (t a =25 c, v cc =5v, f=1.0mhz) note : capacitance is periodically sampled and not 100% tested. item symbol test condition min max unit input/output capacitance c i/o v il =0v - 10 pf input capacitance c in v in =0v - 10 pf program/erase characteristics parameter symbol min typ max unit program time t prog - 0.25 1.5 ms number of partial program cycles in the same page nop - - 10 cycles block erase time t bers - 2 10 ms
KM29N32000TS flash memory 8 ac characteristics for operatio note : 1. if ce goes high within 30ns after the rising edge of the last re , r/ b will not return to v ol . 2. the time to ready depends on the value of the pull-up resistor tied r/ b pin. 3. to break the sequential read cycle, ce must be held high for longer than t ceh . parameter symbol min max unit data transfer from cell to register t r - 10 m s ale to re delay(read id) t ar1 150 - ns ale to re delay(read cycle) t ar2 50 - ns ce to re delay( id read) t cr 100 - ns ready to re low t rr 20 - ns re pulse width t rp 30 - ns we high to busy t wb - 100 ns read cycle time t rc 50 - ns re access time t rea - 35 ns re high to output hi-z t rhz 15 30 ns ce high to output hi-z t chz - 20 ns re high hold time t reh 15 - ns output hi-z to re low t ir 0 - ns last re high to busy(at sequential read) t rb - 100 ns ce high to ready(in case of interception by ce at read) (1) t cry - 50 +tr(r/ b ) (2) ns ce high hold time(at the last serial read) (3) t ceh 100 - ns re low to status output t rsto - 35 ns ce low to status output t csto - 45 ns re high to we low t rhw 0 - ns we high to re low t whr 60 - ns erase suspend input to ready t sr - 500 m s re access time(read id) t readid - 35 ns device resetting time (read/program/erase/after erase suspend) t rst - 5/10/500/5 m s ac timing characteristics for command / address / data input parameter symbol min max unit cle set-up time t cls 0 - ns cle hold time t clh 10 - ns ce setup time t cs 0 - ns ce hold time t ch 10 - ns we pulse width t wp 25 - ns ale setup time t als 0 - ns ale hold time t alh 10 - ns data setup time t ds 20 - ns data hold time t dh 10 - ns write cycle time t wc 50 - ns we high hold time t wh 15 - ns
KM29N32000TS flash memory 9 pointer operation of km29n32000 the km29n32000 has three read modes to set the destination of the pointer. the pointer is set to "a" area by the "00h" command, to "b" area by the "01" command, and to "c" area by the "50h" command. table 1 shows the destination of the pointer, and figure 2 shows the block diagram of its operations. example of pointer operation programming "a" area 50h "c" area (1) "a" area program "a" area address / data input 256 byte table 1. destination of the pointer command pointer position area 00h 01h 50h 0 ~ 255 byte 256 ~ 511 byte 512 ~ 527 byte 1st half array(a) 2nd half array(b) spare array(c) (00h plane) "b" area (01h plane) "c" area (50h plane) 256 byte 16 byte "a" "b" "c" internal page buffer pointer select commnad (00h, 01h, 50h) pointer figure 2. block diagram of pointer operation table 2. pointer status after each operation * 01h command is valid just one time when it is used as a pointer for program/erase. operation pointer status after operation program/erase reset power up with previous 00h, device is set to 00h plane with previous 01h, device is set to 00h plane* with previous 50h, device is set to 50h plane "00h" plane("a" area) "00h" plane("a" area) 00h 80h "a" area program 00h "a" area (2) "b" area program "b" area address / data input 01h 80h "a" area program 00h "a" area (3) "c" area program "c" area address / data input 50h 80h "c" area program 10h 80h 10h 10h 80h 10h 10h 80h 10h address / data input address / data input address / data input "a" area program "b" area program "c" area program
KM29N32000TS flash memory 10 * command latch cycle ce we cle ale i/o 0 ~ 7 command * address latch cycle ce we cle ale i/o 0 ~ 7 a 0 ~a 7 a 9 ~a 16 a 17 ~a 21 t cls t cs t clh t ch t wp t als t alh t ds t dh t cls t cs t wc t wc t wp t wp t wh t wh t als t alh t ds t dh t ds t dh t ds t dh t wp
KM29N32000TS flash memory 11 * input data latch cycle ce cle we i/o 0 ~ 7 din 0 din 1 din 511 ale t als t clh t wc t ch t ds t ds t dh t ds t dh t wp t wh t wp t dh t wp * s equential out cycle after read (cle=l, we =h, ale=l) re ce r/ b i/o 0 ~ 7 trhz* dout dout dout t rc t rea t rr t rhz* t rea t reh t rea t chz* t rhz t rp ?
KM29N32000TS flash memory 12 * status read cycle ce we cle re i/o 0 ~ 7 notes : transition is measured 200mv from steady state voltage with load. this parameter is sampled and not 100% tested. 70h status output t cls t clh t cs t wp t ch t ds t dh t rsto t ir t rhz* t chz* t whr t csto t cls read1 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 21 dout n dout n+1 dout n+2 dout n+3 dout 527 column address page(row) address t wb t ar2 t r t rc t rhz t rr t chz t ceh t rb t cry t wc ? ? ?
KM29N32000TS flash memory 13 read1 operation (intercepted by ce ) ce cle r/ b i/o 0 ~ 7 we ale re busy 00h or 01h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 21 dout n dout n+1 dout n+2 dout n+3 page(row) address address column t wb t ar2 t chz t r t rr t rc read2 operation (read one page) ce cle r/ b i/o 0 ~ 7 we ale re 50h a 0 ~ a 7 a 9 ~ a 16 a 17 ~ a 21 dout dout 527 m address a 0 ~ a 3 :valid address a 4 ~ a 7 :don't care 511+m dout 511+m+1 selected row start address m 512 16 t ar2 t r t wb t rr ? ?
KM29N32000TS flash memory 14 sequential row read operation ce cle r/ b i/o 0 ~ 7 we ale re 00h a 0 ~ a 7 busy m output a 9 ~ a 16 a 17 ~ a 21 dout n dout n+1 dout n+2 dout 527 dout 0 dout 1 dout 2 dout 527 busy m+1 output n page program operation ce cle r/ b i/o 0 ~ 7 we ale re 80h 70h i/o 0 din n din din 10h 527 n+1 a 0 ~ a 7 a 17 ~ a 21 a 9 ~ a 16 sequential data input command column address page(row) address 1 up to 528 byte data sequential input program command read status command i/o 0 =0 successful program i/o 0 =1 error in program t prog t wb t wc t wc t wc ? ? ? ? ? ? ? ? ? ?
KM29N32000TS flash memory 15 block erase operation (erase one block) ce cle r/ b i/o 0 ~ 7 we ale re 60h a 17 ~ a 21 a 9 ~ a 16 auto block erase setup command erase command read status command i/o0=1 error in erase doh 70h i/o 0 busy t wb t bers t wc t wc block address i/o0=0 successful erase suspend & resume operation during block erase ce cle r/ b i/o 0 ~ 7 we ale re 60h a 17 ~ a 21 a 9 ~ a 16 auto block erase setup command program/read d0h 70h i/o 0 busy b0h d0h block address resume function are acceptable suspend t wb t rhw t wb t sr i/o 0 =0 successful erase i/o 0 =1 error in erase ?
KM29N32000TS flash memory 16 manufacture & device id read operation ce cle i/o 0 ~ 7 we ale re 90h read id command maker code device code 00h ech note* t reaid note* km29v32000 : e3h km29n32000 : e5h km29w32000 : e3h
KM29N32000TS flash memory 17 device operation page read upon initial device power up, the device defaults to read1 mode. this operation is also initiated by writing 00h to the command reg- ister along with three address cycles. once the command is latched, it does not need to be written for the following page read o pera- tion. three types of operations are available : random read, serial page read and sequential read. the random read mode is enabled when the page address is changed. the 528 bytes of data within the selected page are trans- ferred to the data registers in less than 10 m s(t r ). the cpu can detect the completion of this data transfer(t r ) by analyzing the output of r/ b pin. once the data in a page is loaded into the registers, they may be read out in 50ns cycle time by sequentially pulsing re with ce staying low. high to low transitions of the re clock output the data starting from the selected column address up to the last column address(column 511 or 527 depending on state of se pin). after the data of last column address is clocked out, the next page is automatically selected for sequential read. waiting 10 m s again allows for reading of the selected page. the sequential read operation is terminated by bringing ce high. the way the read1 and read2 commands work is like a pointer set to either the main area or the spare area. the spare area of bytes 512 to 527 may be selectively accessed by writing the read2 command with se pin low. addresses a 0 to a 3 set the starting address of the spare area while addresses a 4 to a 7 are ignored. unless the operation is aborted, the page address is automatically incre- mented for sequential read as in read1 operation and spare sixteen bytes of each page may be sequentially read. the read1 com- mand(00h/01h) is needed to move the pointer back to the main area. figures 3 thru 6 show typical sequence and timings for each read operation. figure 3. read1 operation start add.(3cycle) 00h 01h a 0 ~ a 7 & a 9 ~ a 21 data output(sequential) (00h command) 1st half array 2nd half array ce cle ale r/ b we data field spare field (01h command)* 1st half array 2nd half array data field spare field * after data access on 2nd half array by 01h command, the start pointer is automatically moved to 1st half array (00h) at next cycle. i/o 0 ~ 7 re t r
KM29N32000TS flash memory 18 figure 5. sequential row read1 operation figure 4. read2 operation 50h a 0 ~ a 3 & a 9 ~ a 21 data output(sequential) spare field ce cle ale r/ b we 1st half array 2nd half array data field spare field ( se =l, 00h command) 1st half array 2nd half array data field spare field 00h 01h a 0 ~ a 7 & a 9 ~ a 21 i/o 0 ~ 7 r/ b start add.(3cycle) start add.(3cycle) data output data output data output 1st 2nd nth (528 byte) (528 byte) (a 4 ~ a 7 : don't care) 1st 2nd nth ( se =l, 01h command) 1st half array 2nd half array data field spare field 1st 2nd nth ( se =h, 00h command) 1st half array 2nd half array data field spare field 1st 2nd nth i/o 0 ~ 7 re t r t r t r t r ?
KM29N32000TS flash memory 19 figure 6. sequential read2 operation ( se =fixed low) page program the device is programmed basically on a page basis, but it does allow multiple partial page programming of a byte or consecutive bytes up to 528, in a single page program cycle. the number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed ten. the addressing may be done in any random order in a block. a page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded into the page registe r, fol- lowed by a nonvolatile programming period where the loaded data is programmed into the appropriate cell. serial data loading can be started from 2nd half array. about the pointer operation, please refer to the attached technical notes.the serial data loadin g period begins by inputting the serial data input command(80h), followed by the three cycle address input and then serial data loading. the bytes other than those to be programmed do not need to be loaded. the page program confirm command(10h) initiates the programming process. writing 10h alone without perviously entering the serial data will not initiate the programming process. the internal write controller automatically executes the algorithms and t imings necessary for program and verify, thereby freeing the cpu for other tasks. once the program process starts, the read status regi s- ter command may be entered, with re and ce low, to read the status register. the cpu can detect the completion of a program cycle by monitoring the r/ b output, or the status bit(i/o 6 ) of the status register. only the read status command and reset com- mand are valid while programming is in progress. when the page program is complete, the write status bit(i/o 0 ) may be checked(figure 7). the internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. the comm and register remains in read status command mode until another valid command is written to the command register. 50h a 0 ~ a 3 & a 9 ~ a 21 i/o 0 ~ 7 r/ b start add.(3cycle) data output data output data output 2nd nth (16 byte) (16 byte) 1st half array 2nd half array data field spare field 1st 2nd nth (a 4 ~ a 7 : don't care) 1st figure 7. program & read status operation 80h a 0 ~ a 7 & a 9 ~ a 21 address & data input i/o 0 pass 528 byte data 10h 70h fail i/o 0 ~ 7 r/ b t r t r t r t prog ?
KM29N32000TS flash memory 20 figure 8. block erase operation block erase the erase operation can erase on a block(8k byte) basis. block address loading is accomplished in two cycles initiated by an era se setup command(60h). only address a 13 to a 21 is valid while a 9 to a 12 is ignored. the addresses of the block to be erased to ffh. the erase confirm command(d0h) following the block address loading initiates the internal erasing process. this two-step sequence of setup followed by execution ensures that memory contents are not accidentally erased due to external noise condition s. at the rising edge of we after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse repetition where required. if an erase operation error is detected, the internal verify is halted and erase operation is termina ted. when the erase operation is completed, the write status bit(i/o 0 ) may be checked. figure 8 details the sequence. 60h block add. : a 9 ~ a 21 i/o 0 ~ 7 r/ b address input(2cycle) i/o 0 pass d0h 70h fail erase suspend/erase resume the erase suspend allows interruption during any erase operation in order to read or program data to or from another block of memory. once an erase process begins, writing the erase suspend command (b0h) to the command register suspends the internal erase process, and the r/ b signal return to "1". erase suspend status bit will be also set to "1" when the status register is read. at this time, blocks other than the suspended block can be read or programmed. the status register and r/ b operation will function as usual. after the erase resume command is written to it, the erase process is restarted from the beginning of the erasing period. the erase suspend status bit and r/ b will return to "0". refer to figure 9 for operation sequence. figure 9. erase suspend & erase resume operation i/o 0 ~ 7 r/ b d0h 60h b0h block address input erase function start erase function suspend erase function resume d0h t bers
KM29N32000TS flash memory 21 read status the device contains a status register which may be read to find out whether program or erase operation is complete, and whether the program or erase operation completed successfully. after writing 70h command to the command register, a read cycle outputs the contents of the status register to the i/o pins on the falling edge of ce or re , whichever occurs last. this two line control allows the system to poll the progress of each device in multiple memory connections even when r/ b pins are common-wired. re or ce does not need to be toggled for updated status. refer to table 2 for specific status register definitions. the command register remains in status read mode until further commands are issued to it. therefore, if the status register is read during a random r ead cycle, a read command(00h or 50h) should be given before sequential page read cycle. sr status definition i/o 0 program / erase "0" : successful program / erase "1" : error in program / erase i/o 1 reserved for future use "0" i/o 2 "0" i/o 3 "0" i/o 4 "0" i/o 5 erase suspend "0" : erase in progress / completed "1" : suspended i/o 6 device operation "0" : busy "1" : ready i/o 7 write protect "0" : protected "1" : not protected table2. status register definition figure 9. read id operation read id the device contains a product identification mode, initiated by writing 90h to the command register, followed by an address inpu t of 00h. two read cycles sequentially output the manufacture code(ech), and the device code (note*) respectively. the command reg- ister remains in read id mode until further commands are issued to it. figure 9 shows the operation sequence. ce cle i/o 0 ~ 7 ale re we 90h 00 ech note* address. 1 cycle maker code device code t readid t ar1 t cr note* km29v32000 : e3h km29n32000 : e5h km29w32000 : e3h
KM29N32000TS flash memory 22 figure 10. reset operation reset the device offers a reset feature, executed by writing ffh to the command register. when the device is in busy state during rand om read, program or erase modes, the reset operation will abort these operation. the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. internal address registers are cleared to "0"s and data regist ers to "1"s. the command register is cleared to wait for the next command, and the status register is cleared to value c0h when wp is high. refer to table 3 for device status after reset operation. if the device is already in reset state a new reset command will not be accepted to by the command register. the r/ b pin transitions to low for t rst after the reset command is written. reset command is not necessary for normal operation. refer to figure 10 below. table3. device status after power-up after reset operation mode read 1 waiting for next command ffh i/o 0 ~ 7 r/ b t rst data protection the device is designed to offer protection from any involuntary program/erase during power-transitions. an internal voltage dete ctor disables all functions whenever vcc is below about 2v. wp pin provides hardware protection and is recommended to be kept at v il during power-up and power-down as shown in figure 8. the two step command sequence for program/erase provides additional software protection. figure 8. ac waveforms for power transition v cc wp high ? ?
KM29N32000TS flash memory 23 ready/ busy the device has a r/ b output that provides a hardware method of indicating the completion of a page program, erase and random read completion. the r/ b pin is normally high but transitions to low after program or erase command is written to the command reg- ister or random read is begin after address loading. it returns to high when the internal controller has finished the operation. the pin is an open-drain driver thereby allowing two or more r/ b outputs to be or-tied. an appropriate pull-up resister is required for proper operation and the value may be calculated by following equation. rp = v cc r/ b open drain output device gnd v cc (max.) - v ol (max.) i ol + ? i l = note* 8ma + ? i l where i l is the sum of the input currents of all devices tied to the r/ b pin. note* km29v32000 : 3.2v km29n32000 : 5.1v km29w32000 : 5.1v when vcc=3.6~5.5v 3.2v when vcc=2.7~3.6v
KM29N32000TS flash memory 24 package dimensions unit :mm/inch 0~8 0 . 0 0 2 0.805 #1 44(40) lead plastic thin small out-line package type(ii) 0 . 0 5 #22(20) #44(40) #23(21) 0.032 0.35 0.10 0.014 0.004 0.80 0.0315 m i n . 0 . 0 4 7 1 . 2 0 m a x . 0.741 18.81 max. 18.41 0.10 0.725 0.004 +0.10 -0.05 +0.004 -0.002 0.15 0.006 1 0 . 1 6 0 . 4 0 0 44(40) - tsop2 - 400f 0.10 0.004 0.50 0.020 0.25 0.010 typ 0 . 4 5 ~ 0 . 7 5 0 . 0 1 8 ~ 0 . 0 3 0 0 . 0 3 9 0 . 0 0 4 1 . 0 0 0 . 1 0 max 1 1 . 7 6 0 . 2 0 0 . 4 6 3 0 . 0 0 8 ( )

▲Up To Search▲

Price & Availability of KM29N32000TS

	To Download KM29N32000TS Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .